The present invention relates to semiconductor devices including capacitors, especially capacitors in which ferroelectrics or high-κ materials are used for capacitive insulating films, and methods for fabricating the same.
Ferroelectrics or high-κ materials exhibit remanent polarization due to hysteresis properties or high relative dielectric constants. Thus, in the field of nonvolatile memories or DRAM devices, the ferroelectrics or the high-κ materials can substitute for silicon oxide or silicon nitride used for capacitive insulating films included in capacitors of semiconductor devices.
Hereinafter, a known method for fabricating a semiconductor device including a capacitor in which a ferroelectric or a high-κ material is used for a capacitive insulating film will be described with reference to the drawings.
First, as shown in FIG. 19A, a transistor region 103 is defined by an isolation film 102 selectively formed in a semiconductor substrate 101 of silicon. Thereafter, an MOS transistor 104 is formed in the transistor region 103.
Next, as shown in FIG. 19B, a first interlevel dielectric film 105 of silicon dioxide is deposited, and then the surface thereof is planarized. Thereafter, a lower-electrode formation film of platinum is deposited by a sputtering process on the planarized first interlevel dielectric film 105. Subsequently, a ferroelectric film containing strontium, bismuth, tantalum and the like is formed by a spin-on process on the lower-electrode formation film. After the ferroelectric film has been crystallized, an upper-electrode formation film of platinum is deposited by a sputtering process on the ferroelectric film. Thereafter, the upper-electrode formation film, the ferroelectric film and the lower-electrode formation film are dry-etched in this order, thereby forming a lower electrode 106, a capacitive insulating film 107 and an upper electrode 108 out of the lower-electrode formation film, the ferroelectric film and the upper-electrode formation film, respectively, on part of the interlevel dielectric film 105 located over the isolation film 102. In this manner, a capacitor 109 made of the lower electrode 106, the capacitive insulating film 107 and the upper electrode 108 is formed.
Then, as shown in FIG. 19C, a second interlevel dielectric film 110 of silicon dioxide is deposited over the entire surface of the semiconductor substrate 101. Thereafter, a first contact hole 110a for exposing the upper electrode 108 therein and a second contact hole 110b for exposing a doped region of the MOS transistor 104 therein are formed in the second interlevel dielectric film 110.
Then, as shown in FIG. 19D, a metal film containing aluminum as a main component is deposited over the entire surface of the second interlevel dielectric film 110 including the contact holes 110a and 110b. The metal film is patterned, thereby forming a wiring 111 out of the metal film. Thereafter, another wiring layer and a passivation film, for example, are formed.
In the known method for fabricating a semiconductor device, however, the capacitor 109 is formed over the isolation film 102 adjacent to the transistor region 103.
In addition, since the capacitor 109 extends along the principal surface of the semiconductor substrate 101, i.e., has a so-called planar structure, the projected area of the capacitor 109 onto the substrate surface that is enough to ensure a required capacitance is large, resulting in the extremely small effect of reducing a wiring rule for the MOS transistor 104 and the wiring 111.
Therefore, especially the semiconductor device including the capacitor 109 in which a ferroelectric or a high-κ material is used for the capacitive insulating film 107 has a problem that the area of each capacitor, specifically the area of each cell in a semiconductor memory, cannot be reduced.